(1) Field of the Invention
The present invention relates to a method for making semiconductor integrated circuits, and more particularly a method for making metal-insulator-metal (MIM) capacitors and concurrently making resistor structures compatible with a copper (Cu) metallization scheme requiring only a single additional masking step. This simplified method is designed to prevent via punchthrough to the top electrode. This novel method also retains the utilization of the capacitor dielectric layer as an etch-stop layer to prevent overetching the copper bottom plate that causes copper particle, and thereby avoiding additional processing steps. The MIM capacitors can be used in an integrated circuit as anti-fuse devices.
(2) Description of the Prior Art
Capacitors are used for various integrated circuit applications. For example, making metal-insulator-metal (MIM) capacitors can be used for mixed signal (analog/digital circuits) applications and radio frequency (RF) circuits, and can also serve as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution.
In previous generations of semiconductor technology, these capacitors are integrated into the semiconductor circuit when the semiconductor devices are formed on the substrate. For example, the one or two doped patterned polysilicon layers used to make the field effect transistors (FETS) and/or bipolar transistors can also be used to form the capacitors. Alternatively, the capacitors can be fabricated using the multilevels of interconnecting metal patterns (e.g., Al/Cu) used to wire up the individual semiconductor devices (FETs).
In recent years the AlCu metallization has been replaced with copper (Cu) to reduce significantly the resistivity of the conductive metal lines and thereby improve the RC (resistancexc3x97capacitance) delay time for improved circuit performance. By using Cu lines, the resistance in series with MIM capacitors is reduced resulting in a higher figure of merit Q (Xc/R), where Xc is the capacitor reactance expressed in ohms, and R is the resistance (ohms).
Several methods of making MIM capacitors are described in the literature. One method is described in the Interconnect Technology Conference 2000 Proceedings of the IEEE 2000, page 111, in a paper entitled xe2x80x9cSingle Mask Metal-Insulator-Metal (MIS) Capacitor with Copper Damascene Metallization for Sub-0.18 xcexcm Mixed Mode Signal and System-on-a-Chip (SoC) Applicationsxe2x80x9d by R. Liu et al., Lucent Technologies Bell Laboratories in which a Cu damascene process is used to form the bottom electrode and then a Si3N4 dielectric is deposited as the capacitor dielectric and as a barrier layer. A conducting material such as TiN, AlCu/TiN, or Ti/TiN/AlCu/TiN is deposited and is patterned by selective etching to stop on the Si3N4 layer to form the top electrode. The paper does not address forming a metal resistor or making contacts to the top electrode. In the Proceedings of the IEEE/IEDM 2000, page 153, a paper entitled xe2x80x9cIntegration of Thin Film MIM Capacitors and Resistors into Copper Metallization based RF-CMOS and Bi-CMOS Technologiesxe2x80x9d by P. Zurcher et al. of Motorola describes a method for making a MIM capacitor and a metal resistor using a Cu dual-damascene process and forming a bottom electrode of TaN, forming a Si3N4 capacitor dielectric layer and a top electrode also formed from TaN. The bottom electrode TaN layer is also patterned to form resistors. A second damascene process is then used to make contacts to the capacitor top electrode and to the resistor and to the underlying metal layers. Other methods of forming MIM capacitors include a paper by M. Armacost et al. of IBM entitled xe2x80x9cA High Reliability Metal Insulator Metal Capacitor for 0.18 xcexcm Copper Technologyxe2x80x9d in the Proceedings of the IEEE/IEDM 2000, page 157, and in the Proceedings of the IEEE/IEDM 1999, page 849, R. Mahnkopf et al. of Infineon and IBM describe a method for making a MIM capacitor in a Cu dual-damascene metallization scheme in a paper entitled xe2x80x9cxe2x80x98System on a Chipxe2x80x99 Technology Platform for 0.18 xcexcm Digital, Mixed Signal and eDRAM Applications.xe2x80x9d
Several patents have been issued for making MIM capacitors. U.S. Pat. No. 6,117,747 to Shao et al. describes a method that utilizes an additional thin metal layer to form a bottom capacitor plate which extends over the edge of a Cu dual-damascene structure. Ma et al., U.S. Pat. No. 6,329,234 B1, describe a method for making a MIM capacitor structure and concurrently an inductor using a single photoresist mask for high-frequency mixed-signal Rf, CMOS applications compatible with a Cu dual-damascene process. U.S. Pat. No. 6,320,244 B1 to Alers et al. describes a method for integrating MIM capacitors with a Cu dual-damascene process. The capacitor is formed in a recess in an insulating layer over an underlying interconnect structure of the integrated circuit. Tu et al. in U.S. Pat. No. 6,271,084 B1 describe a method for making vertical MIM capacitors using a damascene process in which the vertical sidewalls of the capacitor are used to increase the capacitance.
There is still a need in the semiconductor industry to form metal-insulator-metal (MIM) capacitors with high capacitance while improving process yield and product reliability.
A principal object of the present invention is to fabricate a Metal-Insulator-Metal (MIM) capacitor and concurrently make a resistor structure compatible with a copper (Cu) metallization scheme, requiring only one additional masking step.
A second object of this invention is to avoid particle generation by patterning the top plate by etching down to and partially into an interelectrode dielectric layer thereby avoiding etching the Cu bottom plate.
A third objective of this invention is to use a Cu bottom plate to reduce series resistance and thereby improve the figure of merit Q (Xc/R).
Still another objective is to provide an etch-stop layer on the capacitor top plate to prevent via punchthrough to the top plate when via holes are etched through an overlying insulating layer to the capacitor top plate.
A further objective is to incorporate the MIM capacitor into the circuit design to form an anti-fuse, which can then be shorted by applying a voltage between the capacitor plates that is greater than the dielectric breakdown voltage of the capacitor.
The present invention is a method for making improved MIM capacitors using one additional masking step and is compatible with concurrently making metal resistors. This novel process eliminates damage to the capacitor when making via holes through an insulating layer to the top plate of the capacitor. Since the bottom plate is formed from a low-resistance metal (Cu), the figure of merit Q (Xc/R) is increased significantly. Although the method is described using a dual-damascene process, it should be understood that a single-damascene process can also be used.
In sugary the method of this invention begins by providing a semiconductor substrate having partially completed semiconductor circuits, such as FETs and the like, and includes at least one level of metal interconnections embedded in, and coplanar with a first insulating layer. A dual-damascene process is used to form concurrently the bottom plate of the capacitor integrated with the next level of interconnections. The dual-damascene process comprises forming a first etch-stop layer on the first insulating layer, depositing a second insulating layer, depositing a second etch-stop layer, depositing a third insulating layer. First and second recesses are formed in the third insulating layer to the second etch-stop layer. The first recesses are for capacitor bottom plates, and the second recesses are for metal lines. Next, first via holes are etched in the second etch-stop layer and in the second insulating layer exposed within the recesses to the first etch-stop layer. The second etch-stop layer is removed in the first via holes to the underlying metal interconnections. A conformal first barrier layer is deposited and a first copper seed layer is deposited. A first copper layer is electroplated and polished back to form capacitor bottom plates in the first recesses, and to form the metal lines in the second recesses, and to form interlevel electrical interconnections in the first via holes. A relatively thin capacitor dielectric layer, such as silicon nitride or silicon carbide, is deposited on the second insulating layer and over the capacitor bottom plates. A pre-silicon nitride treatment in ammonium (NH3) followed by a brief exposure to SiH4+NH3 is used prior to the Si3N4 deposition to prevent Cu hillock formation on the capacitor bottom plate. The thickness of the capacitor dielectric layer is used to control the value of the capacitance. A metal layer is deposited on the capacitor dielectric layer, and a third etch-stop layer is deposited on the metal layer for the top plate. A photoresist mask and plasma etching are used to pattern the third etch-stop layer and the metal layer to form the capacitor top plates. For example, the top plates are preferably formed from tantalum (Ta). The etching is terminated in the capacitor dielectric layer (also buffer layer) to prevent etching into the underlying Cu bottom plates. During formation of the capacitor top plates, the etching is terminated (about 100 Angstroms) within the capacitor dielectric layer to avoid overetching into the Cu capacitor bottom plates that would otherwise result in unwanted Cu particle contamination. A key feature of this invention is to use the photoresist masking and plasma etching that form the capacitor top plates to concurrently form the metal resistors. The metal layer for the capacitor top plates and for resistors can be varied in thickness to vary the resistance for design purposes. A relatively thick blanket fourth insulating layer is deposited on the substrate to electrically insulate the underlying metallurgy. Second via holes are etched in the fourth insulating layer to the third etch-stop layer on the capacitor top plates and on the metal resistors. Another key feature is the inclusion of the third etch-stop layer to prevent overetching the second via holes and damaging the capacitors. The thin third etch-stop layer is selectively removed in the second via holes. A single damascene process is used to form interlevel contacts in the second via holes. In this process step a second barrier layer and a second seed layer are deposited, and a second copper layer is electroplated and polished back to form the interlevel contacts (Cu plugs) in the second via holes. To complete the remaining levels of electrical interconnections a standard copper metal-line-and-interconnect process can be used, for example, by repeating the damascene process. Alternatively, a dual-damascene process can be used in which the second via holes and recesses for the metal lines are formed, and then filled with Cu to reduce process costs.